 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| - 1 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc 256mbit gddr2 sdram revision 1.6 april 2005 samsung electronics reserves the right to change products or specification without notice. information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for us e in life support, critical care, m edical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any government al procurement to which special terms or provisions may apply.
- 2 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc revision history revision 1.6 (april 14, 2005) ? modified power-up and initialization sequence on page 22. revision 1.5 (march 04, 2005) ? removed k4n56163qf-gc20/22 from the datasheet revision 1.4 (february 5, 2005) ? added lead-free part number in the datasheet. revision 1.3 (january 5, 2005) ? typo corrected revision 1.2 (december 28, 2004) ? changed the dc characteristics table ? added 50 ohm at the emrs(1) programming table. revision 1.1 (december 1, 2004) ? changed icc2p and icc6 to 10ma revision 1.0 (october 20, 2004) ? dc spec defined. ? changed vdd&vddq of k4n56163qf-gc20/22 from 1.8v+ 0.1v to 2.0v+ 0.1v revision 0.0 (april 29, 2004) - target spec ? defined target specification - 3 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc ? 1.8v + 0.1v power supply for device operation ? 1.8v + 0.1v power supply for i/o interface ? 4 banks operation ? posted cas ? programmable cas letency : 4, 5, 6 and 7 ? programmable additive latency : 0, 1, 2, 3, 4 and 5 ? write latency (wl) = read latency (rl) -1 ? burst legth : 4 and 8 (interleave/nibble sequential) ? programmable sequential/ interleave burst mode general description features ? bi-directional differential data-strobe (single-ended data-strobe is an optional feature) ? off-chip driver (ocd) impedance adjustment ? on die termination ? refresh and self refresh average refesh period 7.8us at lower then t case 85c, 3.9us at 85c < t case < 95 c ? 84 ball fbga 4m x 16bit x 4 ba nks graphic ddr2 synchronous dram with differential data strobe ordering information * k4n56163qf-zc is the lead-free part number. part no. max freq. max data rate interface package K4N56163QF-GC25 400mhz 800mbps/pin sstl 84 ball fbga k4n56163qf-gc30 333mhz 667mbps/pin k4n56163qf-gc37 266mhz 533mbps/pin the 256mb gddr2 sdram chip is organized as 4mbit x 16 i/o x 4banks banks device. this synchronous device achieve high speed graphic double-data-rate transfer rates of up to 1000mb/sec/p in for general applications. the chip is designed to comply with the following key gddr2 sdram featur es such as posted cas with additive latency, write latency = read latency - 1, off-chip driver(ocd) impedance adjustment and on die termination. all of the control and add ress inputs are synchronized with a pair of exte rnally supplied different ial clocks. inputs are latched at the cross point of di fferential clocks (ck rising and ck falling). all i/os are synchronized with a pair of bidirec- tional strobes (dqs and dqs ) in a source synchronous fashio n. a thirteen bit address bus is used to convey row, column, and bank address information in a ras /cas multiplexing style. for example, 256mb(x16) device receive 13/9/2 address- ing. the 256mb gddr2 devices operate with a si ngle 1.8v 0.1v power supply and 1.8v 0.1v vddq. the 256mb gddr2 devices are available in 84ball fbgas(x16). note : the functionality described and the ti ming specifications included in this dat a sheet are for the dll enabled mode of operation. for 4m x 16bit x 4 bank gddr2 sdram - 4 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc pin configuration normal package (top view) a b c d e f g h j k l vdd nc vss ldq6 vssq ldm vddq vddq vddq vssq vssq ldqs ldqs ldq7 ldq0 vddq ldq2 vssq ldq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc nc nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq ldq1 ldq3 ldq4 vddl a1 a3 ba1 vref vss cke we ba0 1 2 3 7 8 9 vdd vss vdd nc vss udq6 vssq udm vddq vddq vssq udq1 udq3 udq4 vddq vddq vssq vssq udqs udqs udq7 udq0 vddq udq2 vssq udq5 nc odt m n p r notes: vddl and vssdl are power and ground for the dll. lt is reco mmended that they are isolat ed on the device from vdd, vddq, vss, and vssq. + + + + + + + + + + + 123456789 a b c d e f g h j k l + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m n p r + + + + + + : populated ball + : depopulated ball top view ball locations (see the balls through the package) - 5 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc package dimensions (84 ball fbga) unit : mm 13.00 0.10 11.20 0.80 1.60 11.00 0.10 1 2 3 4 5 6 7 8 9 6.40 0.80 1.60 b c d e f g h j k l a 5.60 (6.15) (0.90) (1.80) 3.20 84- ? 0.45 0.05 ? 0.2 mab 13.00 0.10 11.00 0.10 #a1 0.50 0.05 0.10max 0.35 0.05 max.1.20 m n p r # a1 index mark (optional) - 6 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. cmd, add inputs are samp led on the crossing of the pos- itive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactiva tes, internal clock signals and device input buffers and output drivers. taking cke low provides precharge powe r-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asyn chronous for self refresh exit. cke must be main- tained high throughout read and write acce sses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffe rs, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables terminati on resistance internal to the gddr2 sdram. when enabled, odt is only applied to each dq, udqs/udqs , ldqs/ldqs , udm, and ldm signal for x16 configurations. the odt pin will be ignored if the ext ended mode register (emrs) is pro- grammed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. (l)udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a wr ite access. dm is samp led on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0 - ba1 input bank address inputs: ba0 and ba1 define to which bank an actove, read, write or precharge com- mand is being applied. ba0 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a12 input address inputs: provided the row address for active commands and the column address and auto pre- charge bit for read/write commands to select one loca tion out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide t he op-code during mode register set commands. dq input/ output data input/ output: bi-directional data bus. ldqs,(ldqs ) udqs,(udqs ) input/ output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. ldqs corresponds to the data on dq0-dq7; udqs corresponds to the data on dq8-dq15. the data strobes ldqs and udqs may be used in singl e ended mode or paired with optional complementary signals ldqs and udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disabl es all complementary data strobe signals. nc/rfu no connect: no internal electrical connection is present. v ddq supply dq power supply: 1.8v 0.1v v ssq supply dq ground v ddl supply dll power supply: 1.8v 0.1v v ssl supply dll ground v dd supply power supply: 1.8v 0.1v v ss supply ground v ref supply reference voltage - 7 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc absolute maximum dc ratings ac & dc operating conditions recommended dc operating conditions (sstl - 1.8) symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 1. stresses greater than those listed under ?absolute maximum ratings? may caus e permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions abov e those indicated in the operati onal sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. storage temperature is the case surfac e temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v vddl supply voltage for dll 1.7 1.8 1.9 v 4 vddq supply voltage for output 1.7 1.8 1.9 v 4 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 1,2 vtt termination voltage vref-0.04 vref vref+0.04 v 3 there is no specific device vdd supply vo ltage requirement for sstl-1.8 compliance. however under all conditions vddq must be less than or equal to vdd. 1. the value of vref may be selected by the us er to provide optimum noise margin in t he system. typically the value of vref is expected to be about 0.5 x vddq of t he transmitting device and vref is expec ted to track variations in vddq. 2. peak to peak ac noise on vref may not exceed +/-2% vref(dc). 3. vtt of transmitting device must track vref of receiving device. 4. ac parameters are measured with vdd, vddq and vdddl tied together. - 8 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc operating temper ature condition 1. operating temperature is the case surface temperature on t he center/top side of the dram. for the measurement conditions, please refer to jesd51.2 standard. 2. at 0 - 85 c, operation temperature range are the temperature which all dram specific ation will be supported. 3. at 85 - 95 c operation temperature range, doubling refresh commands in frequency to a 32ms period ( tref i=3.9 us ) is required, and to enter to self refresh mode at th is temperature range, an emrs command is required to change internal refresh rate. input dc logic level input ac logic level ac input test conditions notes: 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units notes toper operating temperature 0 to 95 c 1, 2, 3 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter min. max. units notes vih(ac) ac input logic high vref + 0.250 - v vil(ac) ac input logic low - vref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr - 9 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc differential input ac logic level notes: 1. vid(ac) specifies the input differential voltage |vtr -vcp | required for switchi ng, where vtr is the true input signal (suc h as ck, dqs, ldqs or udqs) and vcp is th e complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to vih(ac) - vil(ac). 2. the typical value of vix(ac) is expec ted to be about 0.5 * vddq of the transmitt ing device and vix(ac) is expected to track variations in vddq . vix(ac) indicates the voltage at which differential input signals must cross. differential ac output parameters note : 1. the typical value of vox(ac) is expec ted to be about 0.5 * vddq of the transmitti ng device and vox(ac) is expected to track varia- tions in vddq . vox(ac) indicates the voltage at which differential out put signals must cross. symbol parameter min. max. units notes vid(ac) ac differential input voltage 0.5 vddq + 0.6 v 1 vix(ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels > - 10 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc ocd default characteristics notes: 1. absolute specifications (0c t case +95c; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v) 2. impedance measurement condition for output source dc current: vddq = 1.7v; vo ut = 1420mv; (vout-vddq)/ioh must be less than 23.4 ohms for values of vout between vddq and vddq- 280mv. impedance measurement condition for out put sink dc current: vddq = 1.7v; vo ut = 280mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. 3. mismatch is absolute value between pull-up and pu ll-dn, both are measured at same temperature and voltage. 4. slew rate measured from v il (ac) to v ih (ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or great er than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. 6. this represents the step size when the ocd is near 18 ohms at nominal conditions across a ll process and represents only the dram uncertainty. output slew rate load : 7. dram output slew rate specification applies to 533mb/ sec/pin, 667mb/sec/pin, 800mb/ sec/pin, 900mbps/sec/pin and 1000mbps/sec/pin speed bins. 8. timing skew due to dram output sl ew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. description parameter min nom max unit notes output impedance 12.6 18 23.4 ohms 1,2 output impedance step size for ocd calibration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 5 v/ns 1,4,5,6,7,8 25 ohms v tt output (v out) reference point - 11 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc dc characteristics note : 1. measured with outputs open and odt off 2. refresh period is 32ms parameter symbol test condition version unit - 25 - 30 - 37 operating current (one bank active) i cc1 burst length=4 t rc t rc (min). i ol =0ma, t cc = t cc (min). dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock cycle 150 135 120 ma precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 10 ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) address and control inputs changing once per clock cycle 45 45 40 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 50 50 50 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock cycle 85 85 80 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks ac tivated. dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock. 300 280 260 ma refresh current i cc5 t rc t rfc 190 180 160 ma self refresh current i cc6 cke 0.2v 10 ma operating current (4bank interleaving) i cc7 burst length=4 t rc t rc (min). i ol =0ma, t cc = t cc (min). dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock cycle 430 400 350 ma (recommended operating conditions unless otherwise noted, 0 c tc 85 c ) - 12 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc input/output capacitance electrical characteristics & ac timing for - 35/30/37 (0 c < t case < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) refresh parameters by device density speed bins and cl, tr cd, trp, trc and tras parameter symbol - 37 - 30 - 25 min max min max units input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 pf parameter symbol 256mb units refresh to active/refresh command time trfc 75 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 s 85 c < t case 95 c 3.9 s speed - 25 - 30 - 37 units bin (cl-trcd-trp) 6-6-6 5-5-5 4-5-5 parameter min min min cas latency 6 5 4 tck tck 2.5 3.0 3.75 ns trcd 6 5 5 tck trp 6 5 5 tck trc 22 18 16 tck tras 16 13 11 tck - 13 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc timing parameters by speed grade (refer to notes for informations rela ted to this table at the bottom) parameter symbol - 25 - 30 - 37 units notes min max min max min max dq output access time from ck/ck tac -400 400 -450 +450 -500 +500 ps dqs output access time from ck/ck tdqsck -350 +350 -400 +400 -450 +450 ps ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min (tcl, tch) x min (tcl, tch) x min (tcl, tch) x ps 20,21 clock cycle time, cl=x tck 2.5 8.0 3.0 8.0 3.75 8.0 ns 24 dq and dm input hold time tdh 175 x 175 x 225 x ps 15,16,17 dq and dm input setup time tds 50 x 50 x 100 x ps 15,16,17 control & address input pulse width for each input tipw 0.6 x 0.6 x 0.6 x tck dq and dm input pulse width for each input tdipw 0.35 x 0.35 x 0.35 x tck data-out high-impedance time from ck/ck thz x tac max x tac max x tac max ps dqs low-impedance time from ck/ ck tlz (dqs) tac min tac max tac min tac max tac min tac max ps 27 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max 2* tacmin tac max ps 27 dqs-dq skew for dqs and associated dq signals tdqsq x 280 x 310 x340 ps 22 dq hold skew factor tqhs x 380 x 410 x440 ps 21 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x thp - tqhs x ps write command to first dqs latching transition tdqss wl -0.25 wl +0.25 wl -0.25 wl +0.25 wl -0.25 wl +0.25 tck dqs input high pulse width tdqsh 0.35 x 0.35 x 0.35 x tck dqs input low pulse width tdqsl 0.35 x 0.35 x 0.35 x tck dqs falling edge to ck setup time tdss 0.2 x 0.2 x 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x 0.2 x 0.2 x tck mode register set command cycle time tmrd 2 x 2 x 2 x tck write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 19 write preamble twpre 0.35 x 0.35 x 0.35 x tck - 14 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc parameter symbol - 25 - 30 - 37 units notes min max min max min max address and control input hold time tih 475 x 475 x475 x ps 14,16,18 address and control input setup time tis 350 x 350 x350 x ps 14,16,18 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck 28 read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 28 active to active command period for 1kb page size products trrd 7.5 x 7.5 x7.5 x ns 12 active to active command period for 2kb page size products trrd 10 x 10 x10 x ns 12 four activate window for 1kb page size products tfaw 37.5 37.5 37.5 ns four activate window for 2kb page size products tfaw 50 50 50 ns cas to cas command delay tccd 2 2 2 tck write recovery time twr 6 x 5 x4 x tck auto precharge write recovery + precharge time tdal twr +trp x twr +trp x twr +trp x tck 23 internal write to read command delay twtr 3 x3 x2 x tck internal read to precharge command delay trtp 3 3 2 tck 11 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 200 200 tck exit precharge power down to any non-read command txp 2 x 2 x 2 x tck exit active power down to read command txard 2 x 2 x 2 x tck 9 exit active power down to read command (slow exit, lower power) txards 6-al 6 - al 6 - al tck 9, 10 cke minimum pulse width (high and low pulse width) t cke 3 3 3 tck odt turn-on delay t aond 332222tck odt turn-on t aon tac (min) tac (max)+0.7 tac (min) tac (max)+0.7 tac (min) tac (max)+1 ns 13, 25 odt turn-on(power-down mode) t aonpd tac (min) +2 3tck+ tac(max) +1 tac (min)+2 2tck+ tac(max) +1 tac (min)+2 2tck+ta c(max)+1 ns odt turn-off delay t aofd 3.5 3.5 2.5 2.5 2.5 2.5 tck - 15 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc general notes, which may a pply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by des ign, but is not necessa rily tested on each device. b. input slew rate for single ended signals is measured from dc-level to ac-level: from vref - 125 mv to vref + 250 mv for risi ng edges and from vref + 125 mv and vref - 250 mv for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv (250mv to -500 mv for falling egdes). c. vid is the magn itude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 2. gddr2 sdram ac timing reference load following figure represents the timing reference load used in definin g the relevant timing parameters of the part. it is not in tended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a productio ntester. system designers will use ibis or other simulation tools to co rrelate the timing reference load to a system environment. manufa cturers will correlate to their production test conditions (generally a c oaxial transmission line terminat ed at the tester electronics) . the output timing reference voltage level for single ended signals is the crosspoint with vtt. the output timing reference volt age level for differential signals is the cro sspoint of the true (e.g. dqs) and the complement (e.g. dqs) signal. parameter symbol - 25 - 30 - 37 units notes min max min max min max odt turn-off t aof tac (min) tac (max)+ 0.6 tac (min) tac (max)+ 0.6 tac (min) tac (max)+ 0.6 ns 26 odt turn-off (power-down mode) t aofpd tac(min)+2 3.5tck+ta c(max)+1 tac(min)+2 2.5tck+ta c(max)+1 tac(min)+ 2 2.5tck+ tac(max)+ 1 ns odt to power down entry latency tanpd 3 3 3 tck odt power down exit latency taxpd 8 8 8 tck ocd drive mode output delay toit 0 12 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck +tih tis+tck +tih tis+tck +tih ns 24 vddq dut dq dqs dqs output v tt = v ddq /2 25 ? timing reference point - 16 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc 3. gddr2 sdram output slew rate test load output slew rate is characterized under the te st conditions as shown in the following figure. 4. differential data strobe gddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing advantages of differential mode are r ealized in system design. the method by which the gddr2 sdra m pin timings are measured is mode dependent. in single ended mode, timi ng relationships are measured relative to the rising or f alling edges of dqs crossing at vref. in differentia l mode, these timing relationships are meas ured relative to the crosspoint of dqs and its complement, dqs . this distinction in timi ng methods is guaranteed by design and characteri zation. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resisor to insure proper operation. 5. ac timings are for linear signal transitions. 6. these parameters guarantee device behavior, but they are not necessarily tested on each device. they may be guaranteed by dev ice design or tester correlation. vddq dut dq dqs, dqs output v tt = v ddq /2 25 ? test point - 17 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc 7. all voltages are referenced to vss. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal reference/supply voltage l evels, but the related specificat ions and device operation are guaranteed for the full voltage range specified. specific notes for de dicated ac parameters 9. user can choose which active power down exit timing to use via mrs(bit 12). txard is expected to be used for fast active pow er down exit timing. txards is expected to be used for slow active power down exit timing. 10. al = additive latency 11. this is a minimum requirement. minimum read to precharge timing is al + bl/2 providi ng the trtp and tras(min) have been satisfied. 12. a minimum of two clocks (2 * tck) is required irrespective of operating frequency 13. timings are guaranteed with command/addr ess input slew rate of 1.0 v/ns. 14. these parameters guarantee device behavio r, but they are not necessarily test ed on each device. they may be guaranteed by device design or tester correlation. 15. timings are guaranteed with data, mask, and (dqs in singled ended mode) input slew rate of 1.0 v/ns. 16. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1v/ns in single ended mode. 17. tds and tdh (data setup and hold) derating 1) input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. 2) input waveform timing is referenced from the input signal crossing at the v ih (dc) level for a rising signal and v il (dc) for a falling signal applied to the device under test. tds v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss dqs dqs tdh tds tdh - 18 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc 18. tis and tih (input setup and hold) derating 1) input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. 2) input waveform timing is referenced from the input signal crossing at the v ih (dc) level for a rising signal and v il (dc) for a falling signal applied to the device under test 19. the maximum limit for this parameter is not a device limit. the dev ice will operate with a greater value for this parameter , but system performance (bus turnaround) will degrade accordingly. 20. min ( tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specif ication limits for tcl and tch). for exampl e, tcl and tch are = 50% of the period, less the half period jitter ( tjit(hp)) of the cloc k source, and less the half period jitter due to crosstalk ( tjit(c rosstalk)) into th e clock traces. 21. tqh = thp ? tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low ( tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tr ansition followed by the worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effect s, and p-channel to n-channel va riation of the output drivers. 22. tdqsq: consists of data pin skew and out put pattern effects, and p-channel to n-c hannel variation of the output drivers as well as output slew rate mismatch between dqs / dqs and associated dq in any given cycle. 23. tdal = (nwr) + ( trp/tck): for each of the terms above, if not alr eady an integer, round to the next highest int eger. tck refers to the application clock period. nwr refers to the twr parameter stored in the mrs. example: for gddr533 at t ck = 3.75 ns with twr programmed to 4 clocks. tdal = 4 + ( 15 ns / 3.75 ns) clocks =4 +(4)clocks=8cloc ks. tis v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss ck ck tih tis tih - 19 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc 24. the clock frequency is allowed to change during self?refresh mode or precharge pow er-down mode. in case of clock frequency change during precharge power-down, a s pecific procedure is required as described in gddr2 device operation 25. odt turn on time min is when the device leaves high impedance and od t resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 26. odt turn off time min is when the dev ice starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. 27. thz and tlz transitions occur in the sa me access time as valid data transitions. these parameters are referenced to a speci fic volt- age level which specifies when the device outpu t is no longer driving (thz), or begins driving (tlz) . following figure shows a method to calculate the point when device is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different vo ltages. the actual voltage measurement points are not critical as long as t he calculation is consistent. 28. trpst end point and trpre begin point are not referenced to a specific voltage level but spec ify when the device output is no longer driving (trpst), or begins driving (trpre). following figure shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (t rpre) by measuring the signal at two diff erent voltages. the actual voltage measure ment points are not critical as long as the calculation is consistent. these notes are referenced to the ?timing parameters by speed grade? tables for gddr2-533/667 and gddr2-800. thz trpst end point t1 t2 voh + x mv voh + 2x mv vol + 2x mv vol + x mv tlz trpre begin poin t t2 t1 vtt + 2x mv vtt + x mv vtt - x mv vtt - 2x mv tlz,trpre begin point = 2*t1-t2 thz,trpst end point = 2*t1-t2 - 20 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc gddr2 sdram device operation & timing diagram - 21 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc self idle setting emrs bank precharging power writing act rda read srf ref ckel mrs ckeh ckeh ckel write automatic sequence command sequence rda wra read pr, pra pr refreshing refreshing down power down active with rda reading with wra active precharge reading writing pr(a) = precharge (all) mrs = (extended) mode register set srf = enter self refresh ref = refresh ckel = cke low, enter power down ckeh = cke high, exit power down, exit self refresh act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) note: use caution with this diagram. it is indented to provide a floorplan of the possible state transitions simplified state diagram functional description all banks precharged activating ckeh read write ckel mrs ckel sequence initialization ocd calibration ckel ckel ckel autoprecharge autoprecharge pr, pra pr, pra and the commands to control them, no t all details. in particular situations involving more than one bank, enabling/disabling on-die termination, power down en try/exit - among other things - are not captured in full detail. - 22 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc basic functionality read and write accesses to the gddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 se lect the bank; a0-a12 select the row). the address bits reg- istered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. prior to normal operation, the gddr2 sdram must be initiali zed. the following sections provide detailed information cov- ering device initialization, register definiti on, command descriptions and device operation. power up and initialization gddr2 sdrams must be powered up and initialized in a pr edefined manner. operational procedures other than those specified may result in undefined operation. power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*vddq and odt *1 at a low state (all other inputs may be unde- fined.) the power voltage ramps are without any slope reversal, ramp time must be no greater than 20ms; and during the ramp, vdd>vddl>vddq and vdd-vddq<0.3 volts. - vdd, vddl and vddq are driven from a single power converter output, and - vtt is limited to 0.95 v max, and - vref tracks vddq/2. or - apply vdd before or at the same time as vddl. - apply vddl before or at the same time as vddq. - apply vddq before or at the same time as vtt & v ref . at least one of these two sets of conditions must be met. 2. start clock and mainta in stable condition. 3. for the minimum of 200 s after stable power and clock(ck, ck ), then apply nop or deselect & take cke high. 4. wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs(2) command, provide ?low? to ba0, ?high? to ba1.) 6. issue emrs(3) command. (to issue emrs(3) command, provide ?high? to ba0 and ba1.) 7. issue emrs to enable dll. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1 and a12.) 8. issue a mode register set command for ?dll reset?. (to issue dll reset command, provide "high" to a8 and "low" to ba0-1) 9. issue precharge all command. 10. issue 2 or more auto-refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll. 12. at least 200 clocks afte r step 8, execute ocd ca libration ( off chip driv er impedance adjustment ). if ocd calibration is not used, emrs ocd def ault command (a9=a8= a7=1) followed by emrs ocd - 23 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc 1. calibration mode exit command (a9=a8=a7=0) must be issued with other operating parameters of emrs. 2. the gddr2 sdram is now ready for normal operation. *1) to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. programming the mode register for application flexibility, burst length, burst type, cas latency, dll reset function, wr ite recovery time(twr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable func- tion, driver impedance, additive cas latency, odt(on die termination), single-ended stro be, and ocd(off chip driver impedance adjustment) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register(mr) or ex tended mode registers(emr(#)) can be altered by re-exe- cuting the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variables must be redefined when the mrs or emrs commands are issued. mrs, emrs and reset dll do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. initialization sequence after power up /ck ck cke command pre all pre all emrs mrs ref ref mrs emrs emrs any cmd dll enable dll reset ocd default ocd cal. mode exit follow ocd flowchart 400ns trfc trfc trp trp tmrd tmrd tmrd toit min. 200 cycle nop odt tcl tch tis v ih (ac) - 24 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc gddr2 sdram mode register set (mrs) the mode register stores the data for controlling the vari ous operating modes of gddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, twr and various vend or specific options to make gddr2 sdram useful for various applications. the default value of the mode re gister is not defined, therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba0 and ba1, while controlling the state of address pins a0 ~ a15. the gddr2 sdram should be in all bank precharge with cke already high prior to writing in to the mode register. the mode register set command cycle time (tmrd) is required to com- plete the write operation to the mode re gister. the mode register contents ca n be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the prec harge state. the mode register is divided into various fields depending on functionality. burst leng th is defined by a0 ~ a2 with options of 4 and 8 bit burst lengths. the burst length decodes are compatible with gddr sdram. burst address sequence type is defined by a3, cas latency is defined by a4 ~ a6. the gddr2 doesn?t support half clock latency mode. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. write recovery time twr is defined by a9 ~ a11. refer to the table for specific codes. *1 : a13 is reserved for future use and must be programmed to 0 when setting the mode register. ba2 and a14 are not used for 512mb, but used for 1gb and 2gb gddr2 sdrams. a15 is reserved for future usage. *2 : wr(write recovery for autoprecharge) mi n is determined by tck max and wr max is det ermined by tck min. wr in clock cycles is calculated by dividing twr (in ns) by tck (i n ns) and rounding up a non-integer value to the next integer (wr[cycles] = twr( ns)/tck(ns)). the mode regist er must be programmed to this value. th is is also used with trp to determin e tdal. cas latency a6 a5 a4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 100 4 101 5 110 6 111 7 burst length a2 a1 a0 burst length 010 4 011 8 burst type a3 type 0 sequential 1 interleave ba 1 ba 0 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ba1 ba0 mrs mode 00 mrs 01 emrs (1) 1 0 emrs (2) : reserved 1 1 emrs (3) : reserved dll a8 dll reset 0no 1yes test mode a7 mode 0normal 1test rfu 0 pd twr dll tm cas latency bt burst length a12 active power down exit time 0 fast exit (use txard) 1 slow exit (use txards) write recovery for auto precharge a11 a10 a9 mrs select 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 011 4 100 5 101 6 110 7 111 8 - 25 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc gddr2 sdram extended mode register set emrs(1) the extended mode register(1) stores the data for enabling or disabling the dll, output driver strength, odt value selec- tion and additive latency. the default va lue of the extended mode register is not defined, therefore the extended mode reg- ister must be written after power-up for proper operation. th e extended mode register is wr itten by asserting low on cs , ras , cas , we and high on ba0, while controlling the states of address pins a0 ~ a12. the gddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (tmrd) must be satisf ied to complete the write oper ation to the exten ded mode register. mo de register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data-output driver. a3~a5 determines the additive latency, a2 and a6 are used for odt value selection, a7~a9 are used for ocd control, a10 is used for dqs# disable. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh oper ation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur befo re a read command can be issu ed to allow time for the inte rnal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tac or tdqsck parame- ters. - 26 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc emrs (1) programming a0 dll enable 0 enable 1 disable a5 a4 a3 additive latency 000 0 001 1 010 2 011 3 100 4 101 5 1 1 0 reserved 1 1 1 reserved a: when adjust mode is issued, al from previously set value must be applied. b: after setting to default, ocd mode needs to be exited by setting a9-a7 to 000. refer to the following 3.2.2.3 section for detailed information a9 a8 a7 ocd calibration program 0 0 0 ocd calibration mode exit; maintain setting 0 0 1 drive(1) 0 1 0 drive(0) 100 adjust mode a 111 ocd calibration default b a1 output driver impedance control driver size 0 normal 100% 1 weak 60% a10 dqs 0 enable 1 disable a6 a2 r tt ( nominal ) 0 0 odt disabled 0 1 75 ohm 1 0 150 ohm 1 1 50 ohm ba1 ba0 mrs mode 00 mrs 01 emrs(1) 1 0 emrs(2): reserved 1 1 emrs(3): reserved a12 qoff (optional) a a. outputs disabled - dqs, dqss, dqs s . this feature is used in conjunction with dimm idd meaurements when iddq is not desired to be included. 0 output buffer enabled 1 output buffer disabled a10 (dqs enable) strobe function matrix dqs dqs 0 (enable) dqs dqs 1 (disable) dqs hi-z ba 1 ba 0 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 1 qoff 0 dqs ocd program rtt additive latency rtt d.i.c dll - 27 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc emrs(2) programming *1 : the rest bits in emrs(2) is reserved for future us e and all bits except a0, a1, a2, a7and ba0, ba1, must be pro- grammed to 0 when setting the m ode register during initialization. . *2 : if pasr (partial array self refres h) is enabled, data located in areas of the array beyond the specified location will be loast if self refresh is entered. da ta integrity will be maintained if tref conditions are met and no self refresh com- mand is issued. pasr is supported fr om the device of 90nm technology(512m b c-die, 256mb g-die, 1gb a-die). *1 : all bits in emrs(3) except ba0 and ba1 are reserved fo r future use and must be programmed to 0 when setting the mode register during initialization. address field extended mode register(2) ba1 ba0 mrs mode 00 mrs 01 emrs(1) 10 emrs(2) 1 1 emrs(3): reserved a7 high temperature self-refresh rate enable 1 enable 0 disable a2 a1 a0 partial array self refresh for 4 banks 000 full array 0 0 1 half array(ba[1:0]=00&01) 0 1 0 quarter array(ba[1:0]=00) 0 1 1 not defined 1 0 0 3/4 array(ba[1:0]=01, 10&11) 1 0 1 half array(ba[1:0]=10&11) 1 1 0 quarter array(ba[1:0]=11) 1 1 1 not defined a2 a1 a0 partial array self refresh for 8 banks 0 0 0 full array 0 0 1 half array(ba[2:0]=000,001,010,&011) 0 1 0 quarter array(ba[2:0]=000&001) 0 1 1 1/8th array(ba[2:0]=000) 1 0 0 3/4 array(ba[2:0]=010,011,100,101,110,&111) 1 0 1 half array(ba[2:0]=100,101,110,&111) 1 1 0 quarter array(ba[2:0]=110&111) 1 1 1 1/8th array(ba[2:0]=111) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 1 0 *1 0 *1 srf 0 *1 psar *2 emrs(3) progra mming: reserved * 1 address field extended mode register(3) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 11 0 *1 - 28 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc off-chip driver (ocd) impedance adjustment gddr2 sdram supports driver calibration feature and the flow chart below is an example of sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and odt (on die termination) should be carefully controlled depend- ing on system environment. start emrs: drive(1) dq & dqs high; dqs low test emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: drive(0) dq & dqs low; dqs high test emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit end all ok all ok need calibration need calibration emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit mrs shoud be set before entering o cd impedance adjustment and odt should be carefully controlled depending on system environment - 29 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs mode. in drive mode all outputs are driven out by gddr2 sdram and drive of dqs is dependent on emrs bit en abling dqs operation. in drive(1) mode, all dq, dqs sig- nals are driven high and all dqs signals are driven low. in drive(0) mode, al l dq, dqs signals are driven low and all dqs signals are driven high. in adjust mode, bl = 4 of operation co de data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance val ue of 18 ohms during nominal temperature and voltage condi- tions. output driver characteristics for ocd calibration default are specified in section 6. ocd applies only to normal full strength output drive setting defined by emrs(1) and if half strength is set, ocd default output driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs commands not intended to adjust ocd characte ristics must specify a9-a7 as '000' in order to maintain the default or calibrated value. off- chip-driver program ocd impedance adjust to adjust output driver impedance, controllers must issu e the adjust emrs command along with a 4bit burst code to gddr2 sdram as in the folowing table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive this burst code to al l dqs at the same time. dt0 in the following table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. th e driver output impedance is adjusted for all gddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a giv en gddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and wh en the limit is reached, further increment or decrement code has no effect. the default setting may be any step within t he 16 step range. when adjust mode command is issued, al from previously set value must be applied off- chip-driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqshigh and dqs low 0 1 0 drive(0) dq, dqs low and dqs high 1 0 0 adjust mode 1 1 1 ocd calibration default 4bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0000 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0010 decrease by 1 step nop 0100 nop increase by 1 step 1000 nop decrease by 1 step 0101 increase by 1 step increase by 1 step 0110 decrease by 1 step increase by 1 step - 30 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and tds/tdh should be met as the following timing diagram. for input data pattern for adjustment, dt0 - dt3 is a fixed order and "not affected by mrs addressing mode (ie. sequential or interleave). drive mode drive mode, both drive(1) and drive(0), is used for contro llers to measure gddr2 sdram driver impedance. in this mode, all outputs are driven out toit after ?enter drive mode ? command and all output drivers are turned-off toit after ?ocd calibration mode exit? command as the following timing diagram. 1001 increase by 1 step decrease by 1 step 1010 decrease by 1 step decrease by 1 step other combinations reserved nop nop nop nop emrs d t0 cmd ck dqs_in dq_in tds tdh wl ocd adjust mode ocd calibration mode exit d t1 d t2 d t3 wr emrs nop nop ck dqs dm v il (ac) v il (dc) v ih (ac) v ih (dc) - 31 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc odt (on die termination) on die termination (odt) is a feature that allows a dram to turn on/off termination resistance. for x16 configuration odt is applied to each dq, udqs/udqs , ldqs/ldqs , udm, and ldm signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function is supported for active and standby mo des, and turned off and not supported in self refresh mode. functional representation of odt odt dc electrical characteristics note 1: test conditio n for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i( v il (ac)) respectively. v ih (ac) , v il (ac) , and vddq values defined in sstl_18 measurement definition for vm: measure voltage (v m ) at test pin (midpoint) with no load. parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a 6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6, a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt mismatch tolerance between any pu ll-up/pull-down pair rtt(mis) -3.75 +3.75 % 1 input pin dram v ss qv ss q v dd qv dd q rval2 rval2 rval1 rval1 sw1 sw1 sw2 sw2 selection between sw1 or sw2 is determined by ? r tt (nominal)? in emrs termination included on all dqs, dm, dqs and dqs pins. switch sw1 or sw2 is enabled by odt pin. target r tt ( ohm) = (rval1) / 2 or (rval2) / 2 input buffer rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) delta vm = 2 x vm vddq x 100% - 1 - 32 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc odt timing for active/standby mode odt timing for powerdown mode t0 t1 t2 t3 t4 t5 t aond ck ck cke odt internal term res. t6 t aofd t is t is t aon,min t aon,max t aof,min t aof,max r tt v ih (ac) v il (ac) t0 t1 t2 t3 t4 t5 ck ck cke odt internal term res. t6 t is t is t aonpd,min t aofpd,max t aonpd,max t aofpd,min r tt v il (ac) v ih (ac) - 33 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc odt timing mode switch at entering power down mode t-5 t-4 t-3 t-2 t-1 t0 ck ck t1 cke odt internal te r m r e s . t is t aofd rtt t is rtt t2 t3 t4 odt internal term res. active & standby mode timings to be applied. power down mode timings to be applied. t aofpdmax t is odt internal term res. t is t aond rtt t is rtt odt internal term res. active & standby mode timings to be applied. power down mode timings to be applied. t aonpdmax t anpd entering slow exit active power down mode or precharge power down mode. v il (ac) v il (ac) v ih (ac) v ih (ac) - 34 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc odt timing mode switch at exiting power down mode t0 t1 t4 t5 t6 t7 ck ck t8 cke odt internal te r m r e s . t is t aofpdmax rtt t is t is rtt t9 t10 t11 odt internal term res. t axpd active & standby mode timings to be applied. power down mode timings to be applied. exiting from slow active power down mode or precharge power down mode. t aofd internal term res. t is rtt odt active & standby mode timings to be applied. t aond internal te r m r e s . rtt odt t aonpdmax t is power down mode timings to be applied. v ih (ac) v il (ac) v il (ac) v ih (ac) v ih (ac) - 35 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba0 and ba1 are used to select the desired bank. the row address a0 through a12 is used to deter- mine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank acti ve command, the gddr2 sdram can accept a read or write command on the following clock cycle. if a r/w command is issued to a bank t hat has not satisfied the trcdmin specifica- tion, then additive latency must be programmed into the device to delay when the r/w command is internally issued to the device. the additive latency value must be chosen to assure trcdmin is satisfied. additive latenc ies of 0, 1, 2, 3, 4, 5 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the minimum time interval between succe ssive bank activate co mmands to the same bank is dete rmined by the ras cycle time of the device (t rc ). the minimum time in terval between bank activate commands is t rrd . bank activate command cycle: trcd = 3, al = 2, trp = 3, trrd = 2, tccd = 2 address ck / ck t0 t2 t1 t3 tn tn+1 tn+2 tn+3 command bank a row addr. bank a activate bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internal ras -cas delay (>= t rcdmin ) : ?h? or ?l? ras cycle time ( >= t rc ) additive latency delay ( al ) read a post cas bank b row addr. bank b activate bank b col. addr. read b post cas bank a bank a precharge bank b addr. bank b precharge bank a row addr. active bank a ras - ras delay time ( >= t rrd ) read begins rcd =1 addr. bank active (>= t ras ) bank precharge time ( >= t rp ) cas -cas delay time ( t ccd ) - 36 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defin ed at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the gddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles . the boundary of the burst cycle is stri ctly restricted to specific segments of the page length. for example, the 32mbit x 4 i/o x 4 bank chip has a page length of 2048 bits (defined by ca0-ca9, ca11). the page length of 2048 is divided into 512 or 25 6 uniquely addressable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. a 4-bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column address supplied to the device during the read or write command (ca0- ca9, ca11). the second, third and fourth access will also occu r within this group segment, however, the burst order is a function of the starting addr ess, and the burst sequence. a new burst access must not interrupt the previous 4 bit burst ope ration in case of bl = 4 sett ing. however, in case of bl = 8 setting, two cases of inte rrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. the minimum cas to cas delay is defined by tccd, and is a minimum of 2 clocks for read or write cycles. - 37 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in gddr2 sdram. in this operation, the gddr2 sdram allows a cas read or write command to be issued immediately after the ras bank activate command (or any time during the ras -cas -delay time, trcd, period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas latency (cl). therefore if a user chooses to issu e a r/w command before the t rcdmin, then al (greater than 0) must be written into the emr(1). the write latency (w l) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section) examples of posted cas operation example 1 read followed by a write to the same bank [al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4] example 2 read followed by a write to the same bank [al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2] 0123456789101112 active a-bank read a-bank write a-bank dout0 dout1 dout2 dout3 din0 din1 din2 din3 ck/ck cmd dqs/dqs dq al = 2 -1 > = trcd cl = 3 > = trac wl = rl -1 = 4 rl = al + cl = 5 active a-bank read a-bank write a-bank dout0 dout1 dout2 dout3 din0 din1 din2 din3 al = 0 > = trcd cl = 3 > = trac wl = rl -1 = 2 rl = al + cl = 3 012 34 56 7 89101112 -1 ck/ck cmd dqs/dqs dq - 38 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst mode operation burst mode operation is used to provide a constant fl ow of data to memory locations (w rite cycle), or from memory loca- tions (read cycle). the paramet ers that define how the burs t mode will operate are burst sequence and burst length. gddr2 sdram supports 4 bit burst and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst type, either sequential or interleaved, is programmable and defined by th e address bit 3 (a3) of the mrs, which is similar to the ddr sdram operation. seamless burst read or write operations are supp orted. unlike ddr devices, interruption of a burst read or write cycle during bl = 4 mode op eration is prohibited. howe ver in case of bl = 8 mo de, interruption of a burst read or write operation is limited to two cases, reads interrupt ed by a read, or writes interrupted by a write. therefore the burst stop command is not supported on gddr2 sdram devices. burst length and sequence bl = 4 bl = 8 note: page length is a f unction of i/o organization and column addressin burst length starting address (a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 burst length starting address (a2 a1 a0) sequential addr essing (decimal) interleave addressing (decimal) 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 - 39 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column addre ss for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe out- put (dqs) is driven low 1 clock cycle before valid data (dq) is driven onto the data bu s. the first bit of the burst is synchro - nized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdrams. the al is defined by the extended mode register set (1)(emrs(1)). gddr2 sdram pin timings are specified for either single en ded mode or differen-tial mode depending on the setting of the emrs ?enable dqs? mode bit; timing advantages of differenti al mode are realized in syst em design. the method by which the gddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differen- tial mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this dis- tinction in timing methods is guaranteed by design and char acterization. note that when di fferential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 kohm resis- tor to insure proper operation. t ch t cl ck ck ck dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax q qq burst read operation: rl = 5 (al = 2, cl = 3, bl = 4) cmd nop nop nop nop nop nop nop dqs nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a posted cas al = 2 cl =3 rl = 5 dqs =< t dqsck t0 t2 t1 t3 t4 t5 t6 t7 t8 - 40 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst read operation: rl = 3 (al = 0 and cl = 3, bl = 8) burst read followed by burst write: rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around- time, which is 4 clocks in case of bl = 4 opera tion, 6 clocks in case of bl = 8 operation. cmd nop nop nop nop nop nop nop dqs nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a cas cl =3 rl = 3 dqs =< t dqsck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 4 dout a 5 dout a 6 dout a 7 cmd post cas nop nop nop nop nop dq?s nop ck/ck t0 tn-1 t1 tn tn+1 tn+2 tn+3 tn+4 tn+5 dout a 0 dout a 1 dout a 2 dout a 3 dqs din a 0 din a 1 din a 2 din a 3 read a wl = rl - 1 = 4 rl =5 post cas write a t rtw (read to write turn around time) nop - 41 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc seamless burst read operation: rl = 5, al = 2, and cl = 3, bl=4 the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, and every 4 clock for bl = 8 operation. this operation is al lowed regardless of same or different banks as long as the banks are activated. cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 read a0 post cas al = 2 cl =3 rl = 5 dqs dout a 4 dout a 5 dout a 6 read a4 post cas - 42 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc reads intrrupted by a read burst read can only be interrupted by another read with 4 bit burst boundary. any other case of read interrupt is not allowed. read burst interrupt timing exam ple: (cl=3, al=0, rl=3, bl=8) notes: 1. read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. read burst of 8 can only be interrupted by another re ad command. read burst interruption by write command or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after previous re ad command. any other re ad burst interrupt timings are prohibited. 4. read burst interruption is allowed to any bank inside dram. 5. read burst with auto precharge enabled is not allowed to interrupt. 6. read burst interruption is allowed by another read with auto precharge command. 7. all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). ck/ck cmd dqs/dqs dqs read b read a nop nop nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b4 b5 b6 b7 - 43 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst write operation the burst write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl -1). a data strobe signal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising e dge of the dqs following the preamble. the tdqss specificat ion must be satisfied for write cycles. the s ubsequent burst bit dat a are issued on succes- sive edges of the dqs until the burst length is completed, wh ich is 4 or 8 bit burst. when the burst has finished, any addi- tional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is the write recovery time (wr). gddr2 sdram pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the emrs ?enable dqs? mode bit; timing advantages of differential mode are re alized in system design. the method by which the gddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoi nt of dqs and its complement, dqs . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resistor to insu re proper operation. burst write operation: rl = 5, wl = 4, twr = 3 (al=2, cl=3), bl = 4 t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh dmin dmin dmin d d d dqs v il (ac) v ih (ac) v il (ac) v ih (ac) v il (dc) v ih (dc) v il (dc) v ih (dc) cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 tn write a posted cas wl = rl - 1 = 4 dqs < = t dqss > = wr din a 0 din a 1 din a 2 din a 3 precharge completion of the burst write - 44 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst write operation: rl = 3, wl = 2, twr = 2 (al=0, cl=3), bl = 4 burst write followed by burst read: rl = 5 (al=2, cl=3), wl = 4, twtr = 2, bl = 4 the minimum number of clock from the burst write command to the burst read command is [cl - 1 + bl/2 + twtr]. this twtr is not a write recovery time (twr) but the time required to transfer the 4b it write data from the input buffer into sense amplifiers in the array. twtr is defined in ac spec table of this data sheet. cmd nop nop nop nop precharge nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 tn write a cas wl = rl - 1 = 2 dqs < = t dqss > = wr din a 0 din a 1 din a 2 din a 3 bank a completion of the burst write activate > = trp cmd nop nop nop nop dq ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 nop dqs di n wl = rl - 1 = 4 post cas read a nop rl =5 al = 2 cl = 3 nop nop write to read = cl - 1 + bl/2 + twtr > = twtr t9 - 45 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc seamless burst write operation: rl = 5, wl = 4, bl=4 the seamless burst write operation is supported by enablin g a write command every other clock for bl = 4 operation, every four clocks for bl = 8 operation. this operation is allowe d regardless of same or different banks as long as the banks are activated. cmd nop nop nop nop nop nop dq?s nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 din a 0 din a 1 din a 2 din a 3 write a0 post cas wl = rl - 1 = 4 dqs write a1 post cas din a 0 din a 1 din a 2 din a 3 - 46 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc writes intrrupted by a write burst write can only be interrupted by an other write with 4 bit burst boundary. any other case of write interrupt is not allowed. write burst interrupt timing example: (cl=3, al=0, rl=3, wl=2, bl=8) notes: 1. write burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. write burst of 8 can only be interrupted by another writ e command. write burst interruption by read command or precharge command is prohibited. 3. write burst interrupt must occur exactly two clocks after previous write command. any other write burst interrupt timings are prohibited. 4. write burst interruption is allo wed to any bank inside dram. 5. write burst with auto precharge enabled is not allowed to interrupt. 6. write burst interruption is allowed by another write with auto precharge command. 7. all command timings are referenced to burst length set in th e mode register. they are not referenced to actual burst. for example, minimum write to precharge timing is wl+b l/2+twr where twr starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end. ck/ck cmd dqs/dqs dqs nop nop nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b5 b6 b7 write b write a b4 - 47 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc write data mask one write data mask (dm) pin for each 8 data bits (dq) will be supported on gddr2 sdrams, consistent with the imple- mentation on gddr sdrams. it has identical timings on write operations as the data bits, and though used in a uni-direc- tional manner, is internally lo aded identically to data bits to in sure matched system timing. dm of x16 bit or ganization is not used during read cycles. data mask timing dqs/ dq dm t ds t dh t ds t dh write ck ck command dqs/dqs dq dm case 2 : max t dqss dqs/dqs dq dm t dqss t dqss t wr data mask func tion, wl=3, al=0, bl = 4 shown case 1 : min t dqss dqs v il (ac) v ih (ac) v il (dc) v ih (dc) v il (ac) v il (dc) v ih (ac) v ih (dc) - 48 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is trig- gered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba0 and ba1 for 256mb are used to define which bank to precharge when the command is issued. bank selection for precharge by address bits burst read operation followed by precharge minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possible precharge, the precharge comma nd may be issued on the rising edge which is ?additive latency(al) + bl/2 clocks? af ter a read command. a new bank active (command) may be issu ed to the same bank after the ras precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that ini- tiates the last 4-bit prefetch of a read to precharge command. this time is called trtp (r ead t o p recharge). for bl = 4 this is the time from the actual read (al after the read co mmand) to precharge command. for bl = 8 this is the time from al + 2 clocks after the read to the precharge command. a10 ba1 ba0 precharged bank(s) remarks low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don?t care don?t care all banks - 49 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc example 1: burst read operation followed by precharge: rl = 4, al = 1, cl = 3, bl = 4, t rtp <= 2 clocks example 2: burst read operation followed by precharge: rl = 4, al = 1, cl = 3, bl = 8, t rtp <= 2 clocks cmd nop nop precharge nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs active bank a > = t rp nop cl =3 nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks al = 1 cl = 3 > = t rtp cmd nop nop nop nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs precharge a nop t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks al = 1 cl = 3 > = t rtp dout a 4 dout a 5 dout a 6 dout a 8 first 4-bit prefetch second 4-bit prefetch nop - 50 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc example 3: burst read operation followed by precharge: rl = 5, al = 2, cl = 3, bl = 4, t rtp <= 2 clocks example 4: burst read operation followed by precharge: rl = 6, al = 2, cl = 4, bl = 4, t rtp <= 2 clocks cmd nop nop nop nop dq?s precharge a ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a posted cas al = 2 cl =3 rl =5 dqs activate bank a > = t rp nop cl =3 nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks > = t rtp cmd nop nop nop nop dq?s precharge a ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =4 rl = 6 dqs activate bank a > = t rp nop cl =4 nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks > = t rtp - 51 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc example 5: burst read operation followed by precharge: rl = 4, al = 0, cl = 4, bl = 8, t rtp > 2 clocks cmd nop nop nop nop dq?s precharge a ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 0 cl =4 rl = 4 dqs activate bank a > = t rp nop nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + 2 clks + max{trtp;2 tck}* * : rounded to next integer dout a 4 dout a 5 dout a 6 dout a 8 first 4-bit prefetch second 4-bit prefetch > = t rtp - 52 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 clks + twr for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (twr) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the twr delay. example 1: burst write followed by precharge: wl = (rl-1) =3, bl=4 example 2: burst write followed by precharge: wl = (rl-1) = 4, bl=4 cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t 8 din a 0 din a 1 din a 2 din a 3 write a posted cas wl = 3 dqs > = t wr precharge a completion of the burst write cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t 9 din a 0 din a 1 din a 2 din a 3 write a posted cas wl = 4 dqs > = t wr precharge a completion of the burst write - 53 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge com- mand or the auto-precharge function. when a read or a write command is given to the gddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the ac tive bank to automatically begin precharge at the earliest possible moment duri ng the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge function is engaged. during auto-pre- charge, a read command will execute as normal with the exceptio n that the active bank will begin to precharge on the ris- ing edge which is cas latency (cl) clock cycles befo re the end of the read burst. auto-precharge also be implemented during write command s. the precharge operation engaged by the auto precharge command will not begin until the last data of the burst wr ite sequence is properly stored in the memory array. this feature allows the precharge operati on to be partially or comp letely hidden during burst read cycles (d ependent upon cas latency) thus improving system perfo rmance for random data access. the ras lockout ci rcuit internally delays the precharge operation until the array restore operation has been completed (tras satisfied) so that the auto precharge com- mand may be issued with any read or write command. burst read with auto precharge if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the gddr2 sdram starts an auto precharge operation on t he rising edge which is (al + bl/2) cycles later than the read wi th ap command if tras(min) and trtp are satisfied. if tras(min) is not satisfied at the edge, the start point of au to-precharge operation will be delayed until tras(min) is satis - fied. if trtp(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until trtp(min) is satis - fied. in case the internal precharge is pushed out by trtp, trp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read_ap to the next activate command becomes al + (trtp + trp)* (see example 2) for bl = 8 the ti me from read_ap to the next activate is al + 2 + (trtp + trp)*, where ?*? means: ?rouded up to the next integer?. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simulta- neously. (1) the ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. (2) the ras cycle time (trc) from the previous bank activation has been satisfied. - 54 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc example 1: burst read operation with auto precharge: rl = 4, al = 1, cl = 3, bl = 8, t rtp <= 2 clocks example 2: burst read operation with auto precharge: rl = 4, al = 1, cl = 3, bl = 4, t rtp > 2 clocks cmd nop nop nop nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks al = 1 cl = 3 > = t rtp dout a 4 dout a 5 dout a 6 dout a 8 first 4-bit prefetch second 4-bit prefetch nop t rtp nop precharge begins here activate bank a > = t rp autoprecharge cmd nop nop nop nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs t0 t2 t1 t3 t4 t5 t6 t7 t 8 > = al + trtp + trp al = 1 cl = 3 4-bit prefetch nop t rtp nop precharge begins here activate bank a autoprecharge t rp - 55 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc example 3: burst read with auto precharge fo llowed by an activation to the same bank (trc limit): rl = 5 (al = 2, cl = 3, internal trcd = 3, bl = 4, t rtp <= 2 clocks) example 4: burst read with auto precharge fo llowed by an activation to the same bank (trp limit): rl = 5 (al = 2, cl = 3, internal trcd = 3, bl = 4, t rtp <= 2 clocks) cmd nop nop nop nop nop dq?s nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =3 rl = 5 dqs activate bank a > = t rp a10 = 1 auto precharge begins cl =3 > = t rc nop > = tras(min) cmd nop nop nop nop nop dq?s nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =3 rl = 5 dqs activate bank a > = t rp a10 = 1 auto precharge begins cl =3 > = t rc nop > = tras(min) - 56 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc burst write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the gddr2 sdram automatically begins precharge operation after the completion of the burst write plus write recovery time (twr). the bank undergoing auto-precharge from the comp letion of the write burst may be reacti vated if the following two conditions are satisfied. (1) the data-in to bank activate delay time (wr + trp) has been satisfied. (2) the ras cycle time (trc) from the previous bank activation has been satisfied. burst write with auto-precharge (trc limit): wl = 2, twr =2, trp=3, bl=4 burst write with auto-precharge (twr + trp): wl = 4, twr =2, trp=3, bl=4 cmd nop nop nop nop nop bank a dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 tm din a 0 din a 1 din a 2 din a 3 wra banka post cas wl =rl - 1 = 2 dqs/dqs a10 = 1 auto precharge begins nop > = wr completion of the burst write active > = t rp > = t rc cmd nop nop nop nop nop bank a dqs nop ck/ck t0 t4 t3 t5 t6 t7 t8 t9 t12 din a 0 din a 1 din a 2 din a 3 wra bank a post cas wl =rl - 1 = 4 dqs/dqs a10 = 1 auto precharge begins nop > = wr completion of the burst write active > = t rp > = t rc - 57 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc precharge & auto precharge clarification notes: 1. the value of trtp is decided by the equation : max( ru - 58 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc self refresh operation the gddr2 sdram device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving od t pin low or using emrs command. once the command is reg- istered, cke must be held low to keep the device in se lf refresh mode. when the gddr2 sdram has entered self refresh mode all of the external signals except cke, are ?don?t care?. since cke is an sstl 2 input, v ref must be main- tained during self refresh operation. the dram initiates a minimum of one one auto refresh command internally within tcke period once it enters self refresh mode. the clock is in ternally disabled during self refresh operation to save power. the minimum time that the gddr2 sdram must remain in self refresh mode is tcke. the user may change the external clock frequency or halt the external clock one clock af ter self-refresh entry is regist ered, however, the clock must be restarted and stable before the device can exit self refres h operation. once self refresh exit command is registered, a delay equal or longer than the txsnr or txsrd must be sa tisfied before a valid comman d can be issued to the device. cke must remain high for the en tire self refresh exit period txsrd for proper operation. upon exit from self refresh, the gddr2 sdram can be put back into self refresh mode afte r txsrd expires. nop or desel ect commands must be regis- tered on each positive clock edge during the self refresh exit interval. odt should also be turned off during txsrd. upon exit from self refresh, the gddr2 sdram requires a minimu m of one extra auto refresh command before it is put back into self refresh mode. - device must be in the ?all banks idle? state prior to entering self refresh mode. - odt must be turned off taofd before entering self refresh mode, and can be turned on again when txsrd timing is satisfied. - txsrd is applied for a read or a read with autoprecharge command - txsnr is applied for any command except a read or a read with autoprecharge command. cmd ck t0 t2 t1 tm tn cke t3 t4 t5 odt self refresh t6 nop taofd ck > = txsnr > = txsrd trp* valid tck tch tcl tis tis tis tis tih nop nop v il (ac) v il (ac) v ih (ac) v il (dc) v ih (ac) v il (ac) v ih (dc) - 59 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc power-down power-down is synchronously entered when cke is registered low (along with nop or deselect command). cke is not allowed to go low while mode register or extended mode regi ster command time, or read or write operation is in progress. cke is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down idd spec will not be applied un til finishing those operations. timing diagrams are shown in the following pages with details for entry into power down. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. dram design guarantees it?s dll in a locked state with an y cke intensive operations as long as dram controller complies with dram specifications. following figures sh ow two examples of cke intensive appli- cations. in both examples, dram maintains dll in a locked state throughout the period. tcke tcke ck ck cke dram maintains dll in locked st ate with intensive cke operation - 60 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is refe rred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power- down or slow exit active power-down, but the dll is kept enabled during fast exit active power-down. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the gddr2 sdram, and odt should be in a valid state but all other input signals are ?don?t care?. cke low must be maintained until tcke has been satisfied. power-down duration is limited by 9 times trefi of the device. the power-down state is synchronously ex ited when cke is registered high (along with a nop or deselect command). cke high must be maintained until tcke has been satisfi ed. a valid, executable command can be applied with power- down exit latency, txp, txar d, or txards, after cke goes high. power-down exit latency is defined at ac spec table of this data sheet. basic power down entry and exit timing diagram t is t is ck/ck cke c ommand valid nop valid don?t care nop t xp, t xard, enter power-down mode t cke t ih t ih t cke t xards valid t ih exit power-down mode t is t ih t cke t ih valid t is v ih (ac) v ih (dc) v il (dc) v ih (ac) v ih (dc) v il (ac) v ih (dc) v ih (ac) - 61 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc ck cmd cke dq dqs cmd cke dq dqs cmd cke dq dqs cmd cke dq dqs rda rda bl=8 pre pre al + bl/2 with trtp = 7.5ns & tras min satisfied al + bl/2 with trtp = 7.5ns & tras min satisfied read to power down entry read with autoprecharge to power down entry ck ck ck start internal precharge al + cl al + cl cke should be kept high unt il the end of burst operation. al + cl bl=4 cke should be kept high cke should be kept high until the end of burst operation. al + cl t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 q q q q q q q q q q q q cke should be kept high until the end of burst operation. until the end of burst operation. q q q q q q q q rd bl=4 rd bl=8 read operation starts with a read command and q q q q t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 dqs dqs dqs dqs - 62 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc cmd cke dq dqs cmd cke dq dqs t0 tm+1 tm+3 tx tx+1 tx+2 ty t1 tm tm+2 ty+1 ty+2 ty+3 wr wr bl=8 cmd cke dq dqs cmd cke dq dqs t0 tm+1 tm+3 tx tx+1 tx+2 tx+3 t1 tm tm+2 tx+4 tx+5 tx+6 wra wra bl=8 pre pre d d d d d d d d d d d d twtr twtr wr*1 d d d d d d d d d d d d wr *1 write to power down entry write with autoprecharge to power down entry ck ck ck ck wl bl=4 bl=4 wl wl wl t0 tm+1 tm+3 tm+4 tm+5 tx tx+1 t1 tm tm+2 tx+2 tx+3 tx+4 ck ck * 1: wr is programmed through mrs t0 tm+1 tm+3 tm+4 tm+5 tx tx+1 t1 tm tm+2 tx+2 tx+3 tx+4 dqs dqs dqs dqs - 63 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc cmd cke cmd cke t0 t3 t5 t6 t7 t8 t9 t1 t2 t4 t10 cmd cke cmd cke cke can go to low one clock after an active command pr or mrs or pra emrs ref act tmrd refresh command to power down entry active command to power down entry precharge/precharge all comma nd to power down entry mrs/emrs command to power down entry ck ck cke can go to low one clock after a precharge or precharge all command cke can go to low one clock af ter an auto-refresh command t11 - 64 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc asynchronous cke low event dram requires cke to be maintained ?high? for all valid o perations as defined in this data sheet. if cke asynchronously drops ?low? during any valid operation dram is not guaranteed to preserve the contents of array. if this event occurs, memory controller must satisfy dram timing specification tdelay before turning off the clocks. stable clocks must exist at the input of dram before cke is raised ?high? again. dram must be fully re-initialized (steps 4 thru 13) as described in initialization sequence. dram is ready for normal operation a fter the initialization sequen ce. see ac timing parametric table for tdelay specification tck ck ck# tdelay cke cke asynchronously drops low clocks can be turned off after this point stable clocks - 65 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc input clock frequency change during precharge power down gddr2 sdram input clock frequency can be changed under following condition: gddr2 sdram is in precharged power down mode. odt must be turned off and cke must be at logic low level. a min- imum of 2 clocks must be waited af ter cke goes low before cl ock frequency may change. sdram input clock fre- quency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. during input clock frequency change, odt and cke mu st be held at stable low levels. once input clock fre- quency is changed, stable new clocks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. depending on new clock frequency an additional mrs com- mand may need to be issued to appropriately set the wr, cl et c.. during dll re-lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. ck cke t0 t4 tx+1 ty ty+1 ty+2 t1 t2 tx ck valid dll nop 200 clocks frequency change ty+3 tz nop nop nop nop reset trp clock frequency change in precharge power down mode txp occurs here taofd stable new clock before power down exit odt is off during dll reset minimum 2 clocks required before changing frequency odt cmd ty+4 - 66 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc no operation command the no operation command should be used in cases when the gddr2 sdram is in an idle or a wait state. the purpose of the no operation command (nop) is to prevent the gddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the ris- ing edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high at the rising edge of the clock, the ras , cas , and we signals become don?t cares. - 67 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc command truth table. command truth table. function cke cs ras cas we ba0 ba1 a11 a10 a9 - a0 notes previous cycle current cycle (extended) mode register set h h l l l l ba op code 1,2 refresh (ref) h h l l l h x x x x 1 self refresh entry h l l l l h x x x x 1 self refresh exit l h hxxx xxxx1,7 lhhh single bank precharge h h l l h l ba x l x 1,2 precharge all banks h h l l h l x x h x 1 bank activate h h l l h h ba row address 1,2 write h h l h l l ba column l column 1,2,3, write with auto precharge h h l h l l ba column h column 1,2,3, read h h l h l h ba column l column 1,2,3 read with auto-precharge h h l h l h ba column h column 1,2,3 no operation h x l h h h x x x x 1 device deselect h x h x x x x x x x 1 power down entry h l hxxx xxxx1,4 lhhh power down exit l h hxxx xxxx1,4 lhhh 1. all gddr2 sdram commands ar e defined by states of cs , ras , cas , we and cke at the rising edge of the clock. 2. bank addresses ba0, ba1, ba2 (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 3. burst reads or writes at bl =4 cannot be terminated or inte rrupted. see sections "reads in terrupted by a read" and "writes in ter- rupted by a write" 4. the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements outlined 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 6. ?x? means ?h or l (but a defined logic level)?. 7. self refresh exit is asynchronous. 8. vref must be maintained during self refresh operation. - 68 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc clock enable (cke) truth table for synchronous transitions current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power down l l x maintain power-down 11, 13, 15 l h deselect or nop power down exit 4, 8, 11,13 self refresh l l x maintain self refresh 11, 15 l h deselect or nop self refresh exit 4, 5,9 bank(s) active h l deselect or nop a ctive power down entry 4,8,10,11,13 all banks idle h l deselect or nop precharge power down entry 4, 8, 10,11,13 h l refresh self refresh entry 6, 9, 11,13 h h refer to the command truth table 7 notes: 1. cke (n) is the logic state of cke at clock edge n; cke (n?1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edg e n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power down and self refresh can not be entered while read or write operations, (extended) mode register set operations or pr echarge opera- tions are in progress. see section "power down" and "sel f refresh command" for a detailed list of restrictions. 11. minimum cke high time is three clocks. ; minimum cke low time is three clocks. 12. the state of odt does not affect the stat es described in this table. the odt functi on is not available during self refresh. 13. the power down does not perform any refresh operations. the dura tion of power down mode is therefore limited by the refresh requirements out- lined. 14. cke must be maintained high while the sdram is in ocd calibration mode . 15. ?x? means ?don?t care (including floating around vref)? in self refresh and power down. however odt must be driven high or l ow in power down if the odt function is enabled (b it a2 or a6 set to ?1? in emrs(1) ). 16. v ref must be maintained during self refresh operation. dm truth table name (functional) dm dqs note write enable - valid 1 write inhibit hx1 1. used to mask write dat a, provided coincident with the corresponding data - 69 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc input signal overshoot/undershoot specification ac overshoot/undershoot specification for address and control pins a0-a15, ba0-ba2, cs , ras , cas , we , cke, odt parameter specification - 37 - 30 maximum peak amplitude allowed for oversh oot area (see following figyre): 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see following figure): 0.9v 0.9v maximum overshoot area above vdd (see following figure). 0.56 v-ns 0.45 v-ns maximum undershoot area below vss (see following figure). 0.56 v-ns 0.45 v-ns ac overshoot/undershoot specification for clock, da ta, strobe, and mask pins dq, dqs, dm, ck, ck parameter specification - 37 -30 maximum peak amplitude allowed for overshoot area (see following figure): 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see following figure): 0.9v 0.9v maximum overshoot area above vddq (s ee following figure): 0.28 v-ns 0.23 v-ns maximum undershoot area below vssq (see following figure): 0.28 v-ns 0.23 v-ns overshoot area maximum amplitude v dd undershoot area maximum amplitude v ss volts (v) ac overshoot and undershoot definition for address and control pins time (ns) overshoot area maximum amplitude v ddq undershoot area maximum amplitude v ssq volts (v) ac overshoot and undershoot definition for clock, data, strobe, and mask pins time (ns) - 70 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc table 1. full strength default pulldown driver characteristics figure 1. gddr2 default pulldown character istics for full strength driver pulldow n current (ma) voltage (v) minimum (23.4 ohms) nominal default low (18 ohms) nominal default high (18 ohms) maximum (12.6 ohms) 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 37.9 60.9 99.1 1.9 101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 vout to vssq (v) 0 20 40 60 80 100 120 pulldown current (ma) maximum nominal default high nominal default low minimum - 71 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc table 2. full strength default pullu p driver characteristics figure 2. gddr2 default pullup characteristic s for full strength output driver pullup current (ma) voltage (v) minimum (23.4 ohms) nominal default low (18 ohms) nominal default high (18 ohms) maximum (12.6 ohms) 0.2 -8.5 -11.1 -11.8 -15.9 0.3 -12.1 -16.0 -17.0 -23.8 0.4 -14.7 -20.3 -22.2 -31.8 0.5 -16.4 -24.0 -27.5 -39.7 0.6 -17.8 -27.2 -32.4 -47.7 0.7 -18.6 -29.8 -36.9 -55.0 0.8 -19.0 -31.9 -40.8 -62.3 0.9 -19.3 -33.4 -44.5 -69.4 1.0 -19.7 -34.6 -47.7 -75.3 1.1 -19.9 -35.5 -50.4 -80.5 1.2 -20.0 -36.2 -52.5 -84.6 1.3 -20.1 -36.8 -54.2 -87.7 1.4 -20.2 -37.2 -55.9 -90.8 1.5 -20.3 -37.7 -57.1 -92.9 1.6 -20.4 -38.0 -58.4 -94.9 1.7 -20.6 -38.4 -59.6 -97.0 1.8 -38.6 -60.8 -99.1 1.9 -101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 vddq to vout (v) -120 -100 -80 -60 -40 -20 0 pullup current (ma) minimum nominal default low nominal default high maximum - 72 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc gddr2 sdram default output driver v?i characteristics gddr2 sdram output driver characteristics are defined for full strength default operation as selected by the emrs1 bits a7-a9 = ?111?. figures 1 and 2 show the driver characteristics graphically, and tables 1 and 2 show the same data in tabu- lar format suitable for input into simulation tools. the driver characteristics evaluation conditions are: nominal default 25 o c (t case), vddq = 1.8 v, typical process minimum tbd o c (t case), vddq = 1.7 v, slow?slow process maximum 0 o c (t case), vddq = 1.9 v, fast?fast process default output driver characteristic curves notes: 1) the full variation in driver current from minimum to maximum process, temperature, and voltage will lie within the outer bounding lines of the v?i curve of figures 1 and 2. 2) it is recommended that the ?typical? ibis v?i cu rve lie within the inner bounding lines of the v?i curves of figures 1 and 2. table 3. full strength calibrated pull down driver characteristics table 4. full strength calibrated pullup driver characteristics gddr2 sdram calibrated output driver v?i characteristics gddr2 sdram output driver characteristics are defined for full strength calibrated operat ion as selected by the proce- dure outlined in off-chip driver (ocd) im pedance adjustment. tables 3 and 4 show the data in tabular format suitable for input into simulation tools. the nominal points represent a de vice at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error n eeds to be added to t hese values. it must be understood that these v-i curves as repre- sented here or in supplier ibis models need to be adjusted to a wider range as a result of any system calibration error. since this is a system specific phenomena, it cannot be quantifie d here. the values in the calibrated ta bles represent just the dram portion of uncertainty while lo oking at one dq only. if the cali calibrated pulldow n current (ma) voltage (v) nominal minimum (21 ohms) nominal low (18.75 ohms) nominal (18 ohms) nominal high (17.25 ohms) nominal maximum (1 5 ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 calibrated pullup current (ma) voltage (v) nominal minimum (21 ohms) nominal low (18.75 ohms) nominal (18 ohms) nominal high (17.25 ohms) nominal maximum (1 5 ohms) 0.2 -9.5 -10.7 -11.4 -11.8 -13.3 0.3 -14.3 -16.0 -16.5 -17.4 -20.0 0.4 -18.7 -21.0 -21.2 -23.0 -27.0 - 73 - rev 1.6 (apr. 2005) 256m gddr2 sdram k4n56163qf-gc bration procedure is used, it is possible to cause th e device to operate outside the bounds of the default device characteristics tables and figures. in such a situation, the timing parameters in the specification cannot be guaran- teed. it is solely up to the system a pplication to ensu re that the device is calibrated between the mini mum and maximum default values at all times. if this can?t be guarant eed by the system ca libration proc edure, re-calibrati on policy, and uncer - tainty with dq to dq variation, then it is recommended that only the default values be used. the nominal maximum and minimum values represent the change in impedance from nomina l low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimu m conditions. if calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. the driver characteristics evaluation conditions are: nominal 25 o c (t case), vddq = 1.8 v, typical process nominal low and nominal high 25 o c (t case), vddq = 1.8 v, any process nominal minimum tbd o c (t case), vddq = 1.7 v, any process nominal maximum 0 o c (t case), vddq = 1.9 v, any process |
Price & Availability of K4N56163QF-GC25
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |